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VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
16 years 7 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
VLSID
2004
IEEE
73views VLSI» more  VLSID 2004»
16 years 7 months ago
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...
Puneet Gupta, Andrew B. Kahng
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
16 years 17 days ago
DraXRouter: global routing in X-Architecture with dynamic resource assignment
In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Archi...
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hon...
ASPDAC
2006
ACM
90views Hardware» more  ASPDAC 2006»
16 years 17 days ago
A routability constrained scan chain ordering technique for test power reduction
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
X.-L. Huang, J.-L. Huang
ASPDAC
2006
ACM
146views Hardware» more  ASPDAC 2006»
16 years 17 days ago
A fixed-die floorplanning algorithm using an analytical approach
— Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the t...
Yong Zhan, Yan Feng, Sachin S. Sapatnekar