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IPPS
2005
IEEE
16 years 1 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
IPPS
2005
IEEE
16 years 23 hour ago
A High-Performance Framework for Sun-to-Earth Space Weather Modeling
The Space Weather Modeling Framework (SWMF) aims at providing software architecture for integrated modeling of different domains of Sun-Earth system and high-performance physics-b...
Ovsei Volberg, Tamas I. Gombosi, Kenneth G. Powell...
ISCAS
2005
IEEE
95views Hardware» more  ISCAS 2005»
16 years 23 hour ago
Area, power, and pin efficient bus transceiver using multi-bit-differential signaling
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
Donald M. Chiarulli, Jason D. Bakos, Joel R. Marti...
ISCAS
2005
IEEE
104views Hardware» more  ISCAS 2005»
16 years 21 hour ago
On the three-dimensional channel routing
— The 3-D channel routing is a fundamental problem on the physical design of 3-D integrated circuits. The 3-D channel is a 3-D grid G and the terminals are vertices of G located ...
Satoshi Tayu, Patrik Hurtig, Yoshiyasu Horikawa, S...
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
16 years 19 hour ago
Thermal-Aware Floorplanning Using Genetic Algorithms
In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while op...
Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, C...