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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 3 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 3 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
ISPD
2010
ACM
207views Hardware» more  ISPD 2010»
16 years 1 months ago
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, ...
Gaurav Ajwani, Chris Chu, Wai-Kei Mak
TEI
2010
ACM
216views Hardware» more  TEI 2010»
16 years 1 months ago
TouchTone: an electronic musical instrument for children with hemiplegic cerebral palsy
Children with hemiplegic cerebral palsy often lack the physical skills to explore their environment independently, express feelings, communicate, and successfully participate in s...
Soumitra Bhat
CIKM
2009
Springer
16 years 1 months ago
Workload-aware trie indices for XML
Well-designed indices can dramatically improve query performance. Including query workload information can produce indices that yield better overall throughput while balancing the...
Yuqing Wu, Sofia Brenes, Hyungdae Yi