3415 search results - page 363 / 683 » Physical Design Refinement: The |
320
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ISCA
2012
IEEE
13 years 9 months ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
153
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GLVLSI
2003
IEEE
16 years 21 hour ago
2003
IEEE
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
170
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
194
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
188
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DASFAA
2003
IEEE
16 years 1 days ago
2003
IEEE
Modern database applications including computeraided design (CAD), medical imaging, or molecular biology impose new requirements on spatial query processing. Particular problems a...