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ISQED
2005
IEEE
116views Hardware» more  ISQED 2005»
16 years 10 days ago
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
Subhrajit Bhattacharya, John A. Darringer, Daniel ...
IPPS
2003
IEEE
16 years 16 hour ago
Expresso and Chips: Creating a Next Generation Microarray Experiment Management System
Expresso is an experiment management system that is designed to assist biologists in planning, executing, and interpreting microarray experiments. It serves as a unifying framewor...
Allan A. Sioson, Jonathan I. Watkinson, Cecilia Va...
ICRA
1999
IEEE
89views Robotics» more  ICRA 1999»
15 years 11 months ago
An Integrated Interface Tool for the Architecture for Agile Assembly
Developing automated assembly systems normally happens in two distinct stages: rst an o -line" stage in which the system is designed and programmed in simulated and then an o...
Jay Gowdy, Zack J. Butler
DAC
2007
ACM
15 years 10 months ago
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips
Microfluidic biochips are revolutionizing many areas of biochemistry and biomedical sciences. Several synthesis tools have recently been proposed for the automated design of bioch...
Tao Xu, Krishnendu Chakrabarty
DAC
2004
ACM
15 years 10 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit