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ACSD
2005
IEEE
144views Hardware» more  ACSD 2005»
16 years 11 days ago
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
IEEECIT
2005
IEEE
16 years 9 days ago
A Performance and Power Co-optimization Approach for Modern Processors
In embedded systems, performance and power are important inter-related issues that cannot be decoupled. Expensive and extensive simulations in a processor design space are usually...
Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh
GECCO
2005
Springer
119views Optimization» more  GECCO 2005»
16 years 7 days ago
Automated re-invention of six patented optical lens systems using genetic programming
This paper describes how genetic programming was used as an invention machine to automatically synthesize complete designs for six optical lens systems that duplicated the functio...
John R. Koza, Sameer H. Al-Sakran, Lee W. Jones
IH
1998
Springer
15 years 11 months ago
Fingerprinting Digital Circuits on Programmable Hardware
Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradig...
John Lach, William H. Mangione-Smith, Miodrag Potk...
DAC
2009
ACM
15 years 10 months ago
RegPlace: a high quality open-source placement framework for structured ASICs
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan