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ICCAD
2001
IEEE
153views Hardware» more  ICCAD 2001»
16 years 3 months ago
The Sizing Rules Method for Analog Integrated Circuit Design
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...
Helmut E. Graeb, Stephan Zizala, Josef Eckmueller,...
MHCI
2009
Springer
16 years 1 months ago
Ubikequitous computing: designing interactive experiences for cyclists
This paper charts the distinctive challenges of designing mobile experiences for cyclists and presents two studies of mobile cyclebased experiences: one a heritage tour; the other...
Duncan Rowland, Martin Flintham, Leif Oppermann, J...
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
16 years 1 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
NOCS
2007
IEEE
16 years 26 days ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
16 years 16 days ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...