3415 search results - page 168 / 683 » Physical Design Refinement: The |
176
click to vote
FPGA
1998
ACM
15 years 10 months ago
1998
ACM
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
147
click to vote
ISSS
1996
IEEE
15 years 10 months ago
1996
IEEE
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
175
click to vote
EUC
2006
Springer
15 years 10 months ago
2006
Springer
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
172
click to vote
ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
188
click to vote
TIM
2010
15 years 1 months ago
2010
In this paper, the authors propose and analyze a network-based control architecture for power-electronicsbuilding-block-based converters. The objective of the proposed approach is ...