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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
15 years 11 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
- For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/So...
Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvi...
AAAI
1994
15 years 8 months ago
Intelligent Automated Grid Generation for Numerical Simulations
Numerical simulation of partial differential equations (PDEs) plays a crucial role in predicting the behavior of physical systems and in modern engineering design. However, in ord...
Ke-Thia Yao, Andrew Gelsey
HUC
2010
Springer
15 years 8 months ago
Surprise trips: a system to augment the natural experience of exploration
Little treasures in nature often go unnoticed by visitors when roaming about in a national park. Ubiquitous technology with its less intrusive character may be apt to enhance this...
Matthias Korn, Raghid Kawash, Lisbet Andersen