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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 5 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
SIGMOD
2010
ACM
308views Database» more  SIGMOD 2010»
15 years 5 months ago
GBLENDER: towards blending visual query formulation and query processing in graph databases
Given a graph database D and a query graph g, an exact subgraph matching query asks for the set S of graphs in D that contain g as a subgraph. This type of queries find important...
Changjiu Jin, Sourav S. Bhowmick, Xiaokui Xiao, Ja...
CASES
2010
ACM
15 years 4 months ago
Resource recycling: putting idle resources to work on a composable accelerator
Mobile computing platforms in the form of smart phones, netbooks, and personal digital assistants have become an integral part of our everyday lives. Moving ahead to the future, m...
Yongjun Park, Hyunchul Park, Scott A. Mahlke, Sukj...
CASES
2010
ACM
15 years 4 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
CASES
2010
ACM
15 years 4 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa