Sciweavers

8347 search results - page 1529 / 1670
» Performance testing of software systems
Sort
View
HIPEAC
2007
Springer
16 years 18 days ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...
HIPEAC
2007
Springer
16 years 18 days ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
LCTRTS
2007
Springer
16 years 17 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
WS
2006
ACM
16 years 11 days ago
Proactive security for mobile messaging networks
The interoperability of IM (Instant Messaging) and SMS (Short Messaging Service) networks allows users to seamlessly use a variety of computing devices from desktops to cellular p...
Abhijit Bose, Kang G. Shin
ISCC
2005
IEEE
107views Communications» more  ISCC 2005»
16 years 16 hour ago
FTSE: The FNP-Like TCAM Searching Engine
As the Internet grows at a very rapid pace, so does the incidence of attack events and documented unlawful intrusions. The Network Intrusion Detection Systems (NIDSes) are designe...
Rong-Tai Liu, Chia-Nan Kao, Hung-Shen Wu, Ming-Cha...
« Prev « First page 1529 / 1670 Last » Next »