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CODES
2007
IEEE
16 years 24 days ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
CODES
2006
IEEE
16 years 16 days ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
LCTRTS
2004
Springer
15 years 11 months ago
Finding effective compilation sequences
Most modern compilers operate by applying a fixed, program-independent sequence of optimizations to all programs. Compiler writers choose a single “compilation sequence”, or ...
L. Almagor, Keith D. Cooper, Alexander Grosul, Tim...
PLDI
2003
ACM
15 years 11 months ago
Linear analysis and optimization of stream programs
As more complex DSP algorithms are realized in practice, an increasing need for high-level stream abstractions that can be compiled without sacrificing efficiency. Toward this en...
Andrew A. Lamb, William Thies, Saman P. Amarasingh...
COMSWARE
2007
IEEE
15 years 10 months ago
QoS-driven middleware for optimum provisioning of location based services
This paper proposes a middleware to reduce the and consistency are usually poor since they depend on cell consumption of network resources and optimize the provision of size; GPS t...
Israel Martín-Escalona, Francisco Barcel&oa...
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