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2006
IEEE
16 years 26 days ago
Design keys to adapt web prefetching algorithms to environment conditions
— This paper focuses on the design process of web prefetching algorithms. The main goal of prefetching techniques in web is to reduce user perceived latency. Since these techniqu...
Josep Domènech, Julio Sahuquillo, Ana Pont,...
IEEEPACT
2006
IEEE
16 years 26 days ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
RTAS
2006
IEEE
16 years 25 days ago
Real-Time Scheduling on Multicore Platforms
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
James H. Anderson, John M. Calandrino, UmaMaheswar...
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
16 years 13 days ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
IPPS
2005
IEEE
16 years 12 days ago
Using Message-Driven Objects to Mask Latency in Grid Computing Applications
One of the attractive features of Grid computing is that resources in geographically distant places can be mobilized to meet computational needs as they arise. A particularly chal...
Gregory A. Koenig, Laxmikant V. Kalé
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