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LCPC
2000
Springer
15 years 10 months ago
Automatic Coarse Grain Task Parallel Processing on SMP Using OpenMP
This paper proposes a simple and efficient implementation method for a hierarchical coarse grain task parallel processing scheme on a SMP machine. OSCAR multigrain parallelizing c...
Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka
CASES
2008
ACM
15 years 9 months ago
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
Chengmo Yang, Alex Orailoglu
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
16 years 1 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
CODES
1999
IEEE
15 years 11 months ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
EMSOFT
2008
Springer
15 years 8 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin
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