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178
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IPPS
2007
IEEE
16 years 28 days ago
2007
IEEE
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
198
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IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
169
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CAV
2009
Springer
16 years 7 months ago
2009
Springer
Abstract. Dynamic Pushdown Networks (DPNs) are a model for parallel programs with (recursive) procedures and process creation. The goal of this paper is to develop generic techniqu...
259
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HPDC
2008
IEEE
16 years 1 months ago
2008
IEEE
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
178
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EUROPAR
1999
Springer
15 years 11 months ago
1999
Springer
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...