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IPPS
2000
IEEE
15 years 11 months ago
Dynamic Data Layouts for Cache-Conscious Factorization of DFT
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Vi...
DAC
2000
ACM
15 years 11 months ago
Fast power grid simulation
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
Sani R. Nassif, Joseph N. Kozhaya
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
15 years 11 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
142
Voted
VLSID
1999
IEEE
88views VLSI» more  VLSID 1999»
15 years 11 months ago
New and Exact Filling Algorithms for Layout Density Control
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layou...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
175
Voted
GPC
2007
Springer
15 years 10 months ago
Assessing Contention Effects on MPI_Alltoall Communications
Abstract. One of the most important collective communication patterns used in scientific applications is the complete exchange, also called All-to-All. Although efficient algorithm...
Luiz Angelo Steffenel, Maxime Martinasso, Denis Tr...