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ISPAN
2000
IEEE
15 years 10 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
ICPPW
2006
IEEE
16 years 5 days ago
Multiple Flows of Control in Migratable Parallel Programs
Many important parallel applications require multiple flows of control to run on a single processor. In this paper, we present a study of four flow-of-control mechanisms: proces...
Gengbin Zheng, Laxmikant V. Kalé, Orion Sky...
IPPS
2000
IEEE
15 years 10 months ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan
CCGRID
2010
IEEE
15 years 7 months ago
Dynamic Auction Mechanism for Cloud Resource Allocation
We propose a dynamic auction mechanism to solve the allocation problem of computation capacity in the environment of cloud computing. Truth-telling property holds when we apply a s...
Wei-Yu Lin, Guan-Yu Lin, Hung-Yu Wei
ISPA
2007
Springer
16 years 9 days ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...