Abstract. In this paper we use colored Petri nets (CPNs) and the supporting CPN Tools for the modeling and performance analysis of grid architectures. The notation of Petri nets is...
Nikola Trcka, Wil M. P. van der Aalst, Carmen Brat...
This paper presents an RTOS-centric hardwareisoftware cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is tha...
The notions of the critical path of events and critical time of an event are key concepts in analyzing the performance of a parallel discrete event simulation. The highest critica...
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...