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CODES
2006
IEEE
16 years 18 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISMIR
2005
Springer
172views Music» more  ISMIR 2005»
16 years 1 days ago
Segmentation and Recognition of Tabla Strokes
A system that segments and labels tabla strokes from real performances is described. Performance is evaluated on a large database taken from three performers under different recor...
Parag Chordia
NSPW
2003
ACM
15 years 11 months ago
SELF: a transparent security extension for ELF binaries
The ability to analyze and modify binaries is often very useful from a security viewpoint. Security operations one would like to perform on binaries include the ability to extract...
Daniel C. DuVarney, V. N. Venkatakrishnan, Sandeep...
IPPS
1999
IEEE
15 years 10 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas
ISCA
1993
IEEE
117views Hardware» more  ISCA 1993»
15 years 10 months ago
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
We evaluate the e ect of processor speed, network bandwidth, and software overhead on the performance of release-consistent software distributed shared memory. We examine ve di er...
Sandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, ...
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