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ARITH
1999
IEEE
15 years 11 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ASYNC
1999
IEEE
136views Hardware» more  ASYNC 1999»
15 years 11 months ago
A Counterflow Pipeline Experiment
The counterflow pipeline architecture [12] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they me...
Bill Coates, Jo C. Ebergen, Jon K. Lexau, Scott Fa...
CODES
1999
IEEE
15 years 11 months ago
Software controlled power management
Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Pow...
Yung-Hsiang Lu, Tajana Simunic, Giovanni De Michel...
168
Voted
ISPD
1999
ACM
108views Hardware» more  ISPD 1999»
15 years 11 months ago
On the behavior of congestion minimization during placement
Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability accurately. In thi...
Maogang Wang, Majid Sarrafzadeh
SIGMOD
1999
ACM
143views Database» more  SIGMOD 1999»
15 years 11 months ago
WALRUS: A Similarity Retrieval Algorithm for Image Databases
Traditional approaches for content-based image querying typically compute a single signature for each image based on color histograms, texture, wavelet transforms etc., and return...
Apostol Natsev, Rajeev Rastogi, Kyuseok Shim
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