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» Performance evaluation of software architectures
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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 5 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
146
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HPCA
2008
IEEE
16 years 7 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
LCTRTS
2009
Springer
16 years 1 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
EMSOFT
2007
Springer
16 years 28 days ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
INFOCOM
2003
IEEE
16 years 1 days ago
Integration of 802.11 and Third-Generation Wireless Data Networks
Abstract— The third-generation (3G) wide area wireless networks and 802.11 local area wireless networks possess complementary characteristics. 3G networks promise to offer always...
Milind M. Buddhikot, Girish P. Chandranmenon, Seun...