Sciweavers

5281 search results - page 689 / 1057
» Performance evaluation of software architectures
Sort
View
WWW
2003
ACM
16 years 7 months ago
SHOCK: communicating with computational messages and automatic private profiles
A computationally enhanced message contains some embedded programmatic components that are interpreted and executed automatically upon receipt. Unlike ordinary text email or insta...
Rajan M. Lukose, Eytan Adar, Joshua R. Tyler, Caes...
POPL
2010
ACM
16 years 4 months ago
On the Verification Problem for Weak Memory Models
We address the verification problem of finite-state concurrent programs running under weak memory models. These models capture the reordering of program (read and write) operation...
Ahmed Bouajjani, Madanlal Musuvathi, Mohamed Faouz...
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
16 years 1 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...
ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
15 years 12 months ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
15 years 11 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...