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ARC
2009
Springer
175views Hardware» more  ARC 2009»
16 years 1 months ago
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
Brendan P. Glackin, Jim Harkin, T. Martin McGinnit...
161
Voted
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
16 years 1 months ago
SecBus: Operating System controlled hierarchical page-based memory bus protection
—This paper presents a new two-levels page-based memory bus protection scheme. A trusted Operating System drives a hardware cryptographic unit and manages security contexts for e...
Lifeng Su, Stephan Courcambeck, Pierre Guillemin, ...
P2P
2009
IEEE
155views Communications» more  P2P 2009»
16 years 1 months ago
ModelNet: Towards a DataCenter Emulation Environment
—ModelNet is a network emulator designed for repeatable, large-scale experimentation with real networked systems. This talk introduces the ideas behind ModelNet that have made it...
Kashi Venkatesh Vishwanath, Amin Vahdat, Ken Yocum...
ISPAN
2008
IEEE
16 years 1 months ago
A Taxonomy of Data Prefetching Mechanisms
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardw...
Surendra Byna, Yong Chen, Xian-He Sun
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
16 years 1 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky