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GLVLSI
2009
IEEE
164views VLSI» more  GLVLSI 2009»
16 years 1 months ago
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da...
AGS
2009
Springer
16 years 1 months ago
Distributed Platform for Large-Scale Agent-Based Simulations
Abstract. We describe a distributed architecture for situated largescale agent-based simulations with predominately local interactions. The approach, implemented in AglobeX Simulat...
David Sislák, Premysl Volf, Michal Jakob, M...
CLUSTER
2008
IEEE
16 years 1 months ago
Gather-arrange-scatter: Node-level request reordering for parallel file systems on multi-core clusters
—Multiple processors or multi-core CPUs are now in common, and the number of processes running concurrently is increasing in a cluster. Each process issues contiguous I/O request...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
SAMOS
2007
Springer
16 years 29 days ago
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration
The Sesame modeling and simulation framework aims at early and thus efficient system-level design space exploration of embedded multimedia system architectures. So far, Sesame onl...
Mark Thompson, Andy D. Pimentel
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 26 days ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...