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VEE
2010
ACM
327views Virtualization» more  VEE 2010»
16 years 1 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
DAC
2007
ACM
16 years 7 months ago
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
Jia Yu, Jingnan Yao, Jun Yang 0002, Laxmi N. Bhuya...
HPCA
2003
IEEE
16 years 7 months ago
Mini-Threads: Increasing TLP on Small-Scale SMT Processors
Several manufacturers have recently announced the first simultaneous-multithreaded processors, both as single CPUs and as components of multi-CPU chips. All are small scale, compr...
Joshua Redstone, Susan J. Eggers, Henry M. Levy
ICCD
2008
IEEE
116views Hardware» more  ICCD 2008»
16 years 3 months ago
Prototyping a hybrid main memory using a virtual machine monitor
— We use a novel virtualization-based approach for computer architecture performance analysis. We present a case study analyzing a hypothetical hybrid main memory, which consists...
Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Br...
SC
2009
ACM
16 years 1 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally