Sciweavers

5281 search results - page 625 / 1057
» Performance evaluation of software architectures
Sort
View
TC
2010
15 years 5 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
DAC
2008
ACM
16 years 7 months ago
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...
Zhen Zhang, Alain Greiner, Sami Taktak
ICCD
2005
IEEE
107views Hardware» more  ICCD 2005»
16 years 3 months ago
Hardware Support for Bulk Data Movement in Server Platforms
Bulk data movement occurs commonly in server workloads and their performance is rather poor on today’s microprocessors. We propose the use of small dedicated copy engines, and p...
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. ...
SASO
2008
IEEE
16 years 1 months ago
Autonomic Request Management Algorithms for Geographically Distributed Internet-Based Systems
Supporting Web-based services through geographical distributed clusters of servers is a common solution to the increasing volume and variability of modern traffic. These architec...
Mauro Andreolini, Sara Casolari, Michele Colajanni
ISCAS
2007
IEEE
114views Hardware» more  ISCAS 2007»
16 years 1 months ago
On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs
Abstract— Parallel time-interleaved analog-to-digital converters (TIADCs) are an attractive architecture to realize low-power and high-speed data conversion. As a drawback of suc...
Stefan Mendel, Christian Vogel