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ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
13 years 9 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
CN
2006
116views more  CN 2006»
15 years 6 months ago
Techniques for available bandwidth measurement in IP networks: A performance comparison
As the Internet grows in scale and complexity, the need for accurate traffic measurement increases. Among the different parameters relevant to traffic measurement, the paper pays ...
Leopoldo Angrisani, Salvatore D'Antonio, Marcello ...
RTCSA
1998
IEEE
15 years 11 months ago
Wait-Free Snapshots in Real-Time Systems: Algorithms and Performance
Snap-shot mechanisms are used to read a globally consistent set of variable values. Such a mechanism can be used to solve a variety of communication and synchronization problems, ...
Andreas Ermedahl, Hans Hansson, Marina Papatrianta...
IEEESCC
2007
IEEE
16 years 1 months ago
A Fault-Tolerant Middleware Architecture for High-Availability Storage Services
Today organizations and business enterprises of all sizes need to deal with unprecedented amounts of digital information, creating challenging demands for mass storage and on-dema...
Sangeetha Seshadri, Ling Liu, Brian F. Cooper, Law...
IPPS
2006
IEEE
16 years 26 days ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...