Sciweavers

5281 search results - page 343 / 1057
» Performance evaluation of software architectures
Sort
View
CODES
2002
IEEE
15 years 11 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
16 years 3 months ago
Design and Implementation of Software Objects in Hardware
This paper proposes a novel approach to implement software object in hardware. Data-Memory mapping schemes are investigated and four hardware object design schemes are proposed an...
Fu-Chiung Cheng, Hung-Chi Wu
CAV
2007
Springer
114views Hardware» more  CAV 2007»
15 years 10 months ago
Configurable Software Verification: Concretizing the Convergence of Model Checking and Program Analysis
In automatic software verification, we have observed a theoretical convergence of model checking and program analysis. In practice, however, model checkers are still mostly concern...
Dirk Beyer, Thomas A. Henzinger, Grégory Th...
ESTIMEDIA
2004
Springer
16 years 5 days ago
Data assignment and access scheduling exploration for multi-layer memory architectures
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
ICCD
2000
IEEE
125views Hardware» more  ICCD 2000»
16 years 3 months ago
Architectural Support for Dynamic Memory Management
Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applicat...
J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan L...