5281 search results - page 256 / 1057 » Performance evaluation of software architectures |
175
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CODES
2004
IEEE
15 years 10 months ago
2004
IEEE
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...
151
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ERSA
2006
15 years 8 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
220
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ICST
2011
IEEE
14 years 10 months ago
2011
IEEE
User input validation is a technique to counter attacks on web applications. In typical client-server architectures, this validation is performed on the client side. This is ineff...
211
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LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
165
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RTSS
1989
IEEE
15 years 10 months ago
1989
IEEE
A new fault tolerant architecture that provides tolerance to a broad scope of hardware, software, and communications faults is being developed. This architecture relies on widely ...