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EUROPAR
2010
Springer
15 years 7 months ago
Transactional Mutex Locks
Mutual exclusion locks limit concurrency but offer low latency. Software transactional memory (STM) typically has higher latency, but scales well. In this paper we propose transac...
Luke Dalessandro, David Dice, Michael L. Scott, Ni...
ICALT
2006
IEEE
16 years 20 days ago
Augmented Learning: Context-Aware Mobile Augmented Reality Architecture for Learning
Mobile Augmented Reality System (MARS) based elearning environments equip a learner with a mobile wearable see-through display that interacts with training/learning software. MARS...
Jayfus T. Doswell
CODES
2005
IEEE
16 years 7 days ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung
CASES
2001
ACM
15 years 10 months ago
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, ...
MKWI
2008
168views Business» more  MKWI 2008»
15 years 8 months ago
Towards Automated Risk Identification in Service-Oriented Architectures
: IT risk management is an important challenge for businesses and software vulnerabilities are a major source of IT risks, as the 2006 CSI/FBI Computer Crime and Security Survey [G...
Lutz Lowis