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» Performance evaluation of software architectures
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ASPLOS
2012
ACM
14 years 2 months ago
Providing safe, user space access to fast, solid state disks
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...
Adrian M. Caulfield, Todor I. Mollov, Louis Alex E...
RTAS
2006
IEEE
16 years 18 days ago
Real-Time Scheduling on Multicore Platforms
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
James H. Anderson, John M. Calandrino, UmaMaheswar...
SIPEW
2009
Springer
127views Hardware» more  SIPEW 2009»
15 years 11 months ago
Investigating Cache Parameters of x86 Family Processors
Abstract. The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance ...
Vlastimil Babka, Petr Tuma
ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Retargetable estimation scheme for DSP architecture selection
— Given the recent wave of innovation and diversification in digital signal processor (DSP) architecture, the need for quickly evaluating the true potential of considered archite...
Naji Ghazal, A. Richard Newton, Jan M. Rabaey
ICDCS
1997
IEEE
15 years 10 months ago
Multi-threading and Remote Latency in Software DSMs
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
Kritchalach Thitikamol, Peter J. Keleher