1491 search results - page 182 / 299 » Performance evaluation of distributed video coding schemes |
149
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IPPS
2006
IEEE
16 years 13 days ago
2006
IEEE
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
201
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ICS
2009
Tsinghua U.
16 years 1 months ago
2009
Tsinghua U.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
162
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TOOLS
2010
IEEE
15 years 4 months ago
2010
IEEE
While traditional approaches to code profiling help locate performance bottlenecks, they offer only limited support for removing these bottlenecks. The main reason is the lack of v...
153
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IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
159
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PERCOM
2006
ACM
16 years 6 months ago
2006
ACM
Tiny embedded systems have not been an ideal outfit for high performance computing due to their constrained resources. Limitations in processing power, battery life, communication ...