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DSN
2007
IEEE
16 years 22 days ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
CODES
2008
IEEE
15 years 8 months ago
Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraint
We study the problem of scheduling repetitive real-time tasks with the Earliest Deadline First (EDF) policy that can guarantee the given maximal temperature constraint. We show th...
Gang Quan, Yan Zhang, William Wiles, Pei Pei
EXPCS
2007
15 years 10 months ago
RiceNIC: a reconfigurable network interface for experimental research and education
The evaluation of new network server architectures is usually performed experimentally using either a simulator or a hardware prototype. Accurate simulation of the hardwaresoftwar...
Jeffrey Shafer, Scott Rixner
PPOPP
2010
ACM
16 years 3 months ago
Is transactional programming actually easier?
Chip multi-processors (CMPs) have become ubiquitous, while tools that ease concurrent programming have not. The promise of increased performance for all applications through ever ...
Christopher J. Rossbach, Owen S. Hofmann, Emmett W...
IPPS
2005
IEEE
15 years 12 months ago
COTS Clusters vs. the Earth Simulator: An Application Study Using IMPACT-3D
In 2002, Japan announced the Earth Simulator—a supercomputer based on low-volume vector processors and a custom network—and reported that computational scientists had used it ...
Daniel G. Chavarría-Miranda, Guohua Jin, Jo...