Sciweavers

13536 search results - page 2578 / 2708
» Performance and control of network systems
Sort
View
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
16 years 23 hour ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
IPPS
2003
IEEE
15 years 11 months ago
Multi-Paradigm Framework for Parallel Image Processing
A software framework for the parallel execution of sequential programs using C++ classes is presented. The functional language Concurrent ML is used to implement the underlying ha...
David J. Johnston, Martin Fleury, Andy C. Downton
DAGM
2003
Springer
15 years 11 months ago
A Computational Model of Early Auditory-Visual Integration
We introduce a computational model of sensor fusion based on the topographic representations of a ”two-microphone and one camera” configuration. Our aim is to perform a robust...
Carsten Schauer, Horst-Michael Gross
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
VISUALIZATION
2000
IEEE
15 years 10 months ago
Extracting regions of interest applying a local watershed transformation
In this paper, we present a new technique for extracting regions of interest (ROI) applying a local watershed transformation. The proposed strategy for computing catchment basins ...
Stanislav L. Stoev, Wolfgang Straßer
« Prev « First page 2578 / 2708 Last » Next »