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CODES
2006
IEEE
16 years 15 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
IPPS
2005
IEEE
16 years 1 days ago
Security Enhancement in InfiniBand Architecture
The InfiniBandTM Architecture (IBA) is a new promising I/O communication standard positioned for building clusters and System Area Networks (SANs). However, the IBA specification ...
Manhee Lee, Eun Jung Kim, Mazin S. Yousif
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 11 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
IM
2007
15 years 6 months ago
Cluster Generation and Labeling for Web Snippets: A Fast, Accurate Hierarchical Solution
This paper describes Armil, a meta-search engine that groups the web snippets returned by auxiliary search engines into disjoint labeled clusters. The cluster labels generated by A...
Filippo Geraci, Marco Pellegrini, Marco Maggini, F...
TC
2011
15 years 1 months ago
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
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