Sciweavers

2180 search results - page 102 / 436
» Performance analysis of concurrent systems with early evalua...
Sort
View
AIPS
2009
15 years 7 months ago
Using the Context-enhanced Additive Heuristic for Temporal and Numeric Planning
Planning systems for real-world applications need the ability to handle concurrency and numeric fluents. Nevertheless, the predominant approach to cope with concurrency followed b...
Patrick Eyerich, Robert Mattmüller, Gabriele ...
QEST
2009
IEEE
16 years 1 months ago
Integrating TPNs and Performance Bound Techniques in ITPN-PerfBound: A New Import Functionality
Abstract—ITPN-PerfBound is a graphical tool for the modeling and performance bound analysis of Interval Time Petri Nets (ITPN), that has been developed within the DrawNET modelin...
Elina Pacini Naumovich, Simona Bernardi
SPAA
2010
ACM
15 years 11 months ago
Implementing and evaluating nested parallel transactions in software transactional memory
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
CDVE
2006
Springer
160views Visualization» more  CDVE 2006»
15 years 10 months ago
Automated Social Network Analysis for Collaborative Work
Inter-networked computers enable virtual collaborative work. In the course of interacting with one another, individuals send and receive messages and files of various sorts. This m...
Larry Korba, Ronggong Song, George Yee, Andrew S. ...
SDL
2003
147views Hardware» more  SDL 2003»
15 years 7 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...