2964 search results - page 475 / 593 » Performance Prediction of a Parallel Simulator |
199
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HOTI
2011
IEEE
14 years 6 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
193
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PCRCW
1997
Springer
15 years 10 months ago
1997
Springer
In recent years, theChaos Project at theUniversityofWashingtonhas analyzed and simulated a dozen routing algorithms. Three new routing algorithms have been invented; of these, the...
198
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PPSN
2000
Springer
15 years 10 months ago
2000
Springer
Abstract. We explore a new general-purpose heuristic for nding highquality solutions to hard optimization problems. The method, called extremal optimization, is inspired by self-or...
139
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IEEEPACT
2008
IEEE
16 years 24 days ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
161
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PDP
2010
IEEE
15 years 10 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...