6709 search results - page 377 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
178
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
175
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ATAL
2008
Springer
15 years 8 months ago
2008
Springer
Due to computational intractability, large scale coordination algorithms are necessarily heuristic and hence require tuning for particular environments. In domains where character...
187
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SDM
2008
SIAM
15 years 8 months ago
2008
SIAM
In this paper we explore private computation built on vector addition and its applications in privacypreserving data mining. Vector addition is a surprisingly general tool for imp...
179
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AHS
2007
IEEE
15 years 10 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
133
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DATE
2010
IEEE
15 years 12 months ago
2010
IEEE
—The super node algorithm performs model order reduction based on physical principles. Although the algorithm provides us with compact models, its passivity has not thoroughly be...