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» Performance Modelling of the Computational Hardware: A Stati...
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DAC
2006
ACM
16 years 7 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
IPPS
2007
IEEE
16 years 1 months ago
Improving Data Access Performance with Server Push Architecture
Data prefetching, where data is fetched before CPU demands for it, has been considered as an effective solution to mask data access latency. However, the current client-initiated ...
Xian-He Sun, Surendra Byna, Yong Chen
176
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CEC
2008
IEEE
15 years 8 months ago
Evolving scale-free topologies using a Gene Regulatory Network model
Abstract-- A novel approach to generating scale-free network topologies is introduced, based on an existing artificial Gene Regulatory Network model. From this model, different int...
Miguel Nicolau, Marc Schoenauer
ICIP
2010
IEEE
15 years 4 months ago
3D video performance segmentation
We present a novel approach that achieves segmentation of subject body parts in 3D videos. 3D video consists in a freeviewpoint video of real-world subjects in motion immersed in ...
Tony Tung, Takashi Matsuyama
FORMATS
2003
Springer
15 years 12 months ago
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
Probabilistic timed automata, a variant of timed automata extended with discrete probability distributions, is a specification formalism suitable for describing both nondeterminis...
Marta Z. Kwiatkowska, Gethin Norman, David Parker,...