6709 search results - page 303 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
162
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ECBS
2008
IEEE
16 years 1 months ago
2008
IEEE
Network designers perform challenging tasks with so many configuration options that it is often hard or even impossible for a human to predict all potentially dangerous situation...
161
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CPE
2000
Springer
15 years 11 months ago
2000
Springer
In this paper we present a tool for the simulation of fluid models of high-speed telecommunication networks. The aim of such a simulator is to evaluate measures which can not be ...
421
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DAC
2012
ACM
13 years 9 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
193
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CAV
2006
Springer
15 years 10 months ago
2006
Springer
Example Guided Abstraction Refinement (CEGAR) [6] framework. A number of wellengineered software model-checkers are available, e.g., SLAM [1] and BLAST [12]. Why build another one?...
162
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GLOBECOM
2006
IEEE
16 years 21 days ago
2006
IEEE
— We consider a ring topology with limited or full switching capability as deployed in high bandwidth metro optical networks and develop a model to estimate the probability of bl...