Sciweavers

6709 search results - page 246 / 1342
» Performance Modelling of the Computational Hardware: A Stati...
Sort
View
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
16 years 18 days ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
15 years 10 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
BMCV
2000
Springer
15 years 11 months ago
Towards a Computational Model for Object Recognition in IT Cortex
First IEEE International Workshop on Biologically Motivated Computer Vision, Seoul, Korea (May 2000). There is considerable evidence that object recognition in primates is based o...
David G. Lowe
FLAIRS
2000
15 years 8 months ago
A Parallel Approach to Modeling Language Learning and Understanding in Young Children
To reduce the complexity of studying a parallel mechanism for natural language learning and understanding which supports both utterance and discourse processing, we propose a comp...
Charles Hannon, Diane J. Cook
ISQED
2009
IEEE
70views Hardware» more  ISQED 2009»
16 years 1 months ago
On-chip transistor characterization arrays with digital interfaces for variability characterization
An on-chip test-and-measurement system with digital interfaces that can perform device-level characterization of large-dense arrays of transistors is demonstrated in 90- and 65-nm...
Simeon Realov, William McLaughlin, Kenneth L. Shep...