6709 search results - page 214 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
171
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SBACPAD
2007
IEEE
16 years 23 days ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
175
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VLSID
2006
IEEE
16 years 6 months ago
2006
IEEE
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
161
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SIGMETRICS
2006
ACM
16 years 13 days ago
2006
ACM
The Erlang formula is known to be insensitive to the holding time distribution beyond the mean. While calls are generally assumed to arrive as a Poisson process, we prove that it ...
174
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ICAC
2005
IEEE
16 years 3 days ago
2005
IEEE
An important problem in resource management for networked resource-sharing systems is the simultaneous allocation of multiple resources to an application. Selfoptimizing systems m...
177
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CODES
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....