6709 search results - page 1116 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
149
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ISCA
2000
IEEE
15 years 11 months ago
2000
IEEE
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
157
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IJES
2006
15 years 6 months ago
2006
Embedded real-time systems must satisfy not only logical functional requirements but also para-functional properties such as timeliness, Quality of Service (QoS) and reliability. W...
214
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
159
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CVPR
2001
IEEE
16 years 8 months ago
2001
IEEE
The dichromatic reflectance model introduced by Shafer [16] predicts that the colour signals of most materials fall on a plane spanned by a vector due to the material and a vector...
173
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CGF
2002
15 years 6 months ago
2002
We extend the standard solution to comic rendering with a comic-style specular component. To minimise the computational overhead associated with this extension, we introduce two o...