6709 search results - page 1085 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
174
click to vote
ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
195
click to vote
IWMM
2010
Springer
15 years 11 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
166
click to vote
ICCAD
1999
IEEE
15 years 11 months ago
1999
IEEE
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
155
click to vote
MICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
188
click to vote
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
- Many electronic systems contain implementations of cryptographic algorithms in order to provide security. It is well known that cryptographic algorithms, irrespective of their th...