6709 search results - page 1017 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
310
click to vote
SASP
2009
IEEE
16 years 1 months ago
2009
IEEE
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
171
click to vote
DAC
2008
ACM
16 years 7 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
183
click to vote
DAC
2004
ACM
16 years 7 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
189
click to vote
CC
2007
Springer
16 years 28 days ago
2007
Springer
As the amount of data used by programs increases due to the growth of hardware storage capacity and computing power, efficient memory usage becomes a key factor for performance. Si...
161
click to vote
ASPDAC
2006
ACM
16 years 22 days ago
2006
ACM
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...