The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
This paper is a report on the 3D Shape Retrieval Constest 2010 (SHREC'10) track on large scale retrieval. This benchmark allows evaluating how wel retrieval algorithms scale ...
Remco C. Veltkamp, Geert-Jan Giezeman, Hannah Bast...
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...