Sciweavers

5564 search results - page 621 / 1113
» Performance Modeling of HPC Applications
Sort
View
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
15 years 8 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston
3DOR
2010
15 years 1 months ago
SHREC'10 Track: Large Scale Retrieval
This paper is a report on the 3D Shape Retrieval Constest 2010 (SHREC'10) track on large scale retrieval. This benchmark allows evaluating how wel retrieval algorithms scale ...
Remco C. Veltkamp, Geert-Jan Giezeman, Hannah Bast...
ECCTD
2011
72views more  ECCTD 2011»
14 years 6 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic
SIGMETRICS
1996
ACM
174views Hardware» more  SIGMETRICS 1996»
15 years 11 months ago
Embra: Fast and Flexible Machine Simulation
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
Emmett Witchel, Mendel Rosenblum
CODES
2005
IEEE
16 years 14 days ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra