4451 search results - page 544 / 891 » Performance Modeling for Entity-Level Simulations |
187
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PATMOS
2005
Springer
16 years 6 days ago
2005
Springer
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
153
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PATMOS
2004
Springer
16 years 2 days ago
2004
Springer
Synchronization between independently clocked regions in a high performance system is often subject to latencies of more than one clock cycle. We show how the latency can be reduce...
170
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ICDCSW
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper focuses on flow control in high-speed networks. Each node in the networks handles its local traffic flow only on the basis of the information it knows, but it is pre...
186
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ICPP
2000
IEEE
15 years 11 months ago
2000
IEEE
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
206
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CODES
1999
IEEE
15 years 11 months ago
1999
IEEE
raction levels of communication models to allow designers to trade off between performance and accuracy. Contrary to [2][3], we present an optimization method which preserves the a...