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CODES
2006
IEEE
16 years 11 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
CODES
2004
IEEE
15 years 10 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ICDE
2003
IEEE
114views Database» more  ICDE 2003»
16 years 7 months ago
Ranked Join Indices
A plethora of data sources contain data entities that could be ordered according to a variety of attributes associated with the entities. Such orderings result effectively in a ra...
Panayiotis Tsaparas, Themistoklis Palpanas, Yannis...
CGO
2004
IEEE
15 years 10 months ago
VHC: Quickly Building an Optimizer for Complex Embedded Architectures
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
Michael Dupré, Nathalie Drach, Olivier Tema...
SUTC
2006
IEEE
16 years 9 days ago
Energy and Communication Efficient Group Key Management Protocol for Hierarchical Sensor Networks
- In this paper, we describe a group key management protocol for hierarchical sensor networks where instead of using pre-deployed keys, each sensor node generates a partial key dyn...
Biswajit Panja, Sanjay Kumar Madria, Bharat K. Bha...