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» Performance Evaluation of IEEE 802.11 DCF Networks
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CODES
2005
IEEE
15 years 11 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICPADS
2005
IEEE
15 years 11 months ago
I/O Processor Allocation for Mesh Cluster Computers
As cluster systems become increasingly popular, more and more parallel applications require need not only computing power but also significant I/O performance. However, the I/O s...
Pangfeng Liu, Chun-Chen Hsu, Jan-Jan Wu
MSS
2003
IEEE
151views Hardware» more  MSS 2003»
15 years 11 months ago
Accurate Modeling of Cache Replacement Policies in a Data Grid
Caching techniques have been used to improve the performance gap of storage hierarchies in computing systems. In data intensive applications that access large data files over wid...
Ekow J. Otoo, Arie Shoshani
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
16 years 3 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
16 years 13 days ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li