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» Performance Evaluation of IEEE 802.11 DCF Networks
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CODES
2006
IEEE
16 years 8 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
P2P
2006
IEEE
153views Communications» more  P2P 2006»
16 years 6 days ago
Internet-Scale Storage Systems under Churn -- A Study of the Steady-State using Markov Models
Content storage in a distributed collaborative environment uses redundancy for better resilience and thus provides good availability and durability. In a peer-to-peer environment,...
Anwitaman Datta, Karl Aberer
ISBI
2004
IEEE
16 years 6 months ago
SCIRun/BioPSE: Integrated Problem Solving Environment for Bioelectric Field Problems and Visualization
SCIRun is a general purpose problem solving environment that seeks to integrate the steps of preparing, executing, and visualizing simulations of physical and biological systems. ...
Robert S. MacLeod, David M. Weinstein, J. Davison ...
HPCA
2009
IEEE
16 years 6 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
NTMS
2009
IEEE
16 years 28 days ago
Q-ESP: A QoS-Compliant Security Protocol to Enrich IPSec Framework
—IPSec is a protocol that allows to make secure connections between branch offices and allows secure VPN accesses. However, the efforts to improve IPSec are still under way; one ...
Mahmoud Mostafa, Anas Abou El Kalam, Christian Fra...